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Instruction set
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#	Item
291	Version 1.0 Thumb Instructions and Kernels David May: April 23, 2013 The Instructions Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2013-04-25 05:29:16 Instruction set architectures Instruction set Minicomputers Processor register Operating system Assembly languages Microcontrollers TI-990 X86 assembly language Computer architecture Computer hardware Central processing unit
292	EN164: Design of Computing Systems Lecture 09: Processor / ISA 2 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:52 Central processing unit MIPS architecture Instruction set 64-bit Processor register Assembly languages Pointer Memory address AN/UYK-8 Computer architecture Instruction set architectures Computing
293	Senior Reduced Fare Registration Centers 0 Senior Reduced Fare Registration Centers Add to Reading List Source URL: rtachicago.org Language: English - Date: 2015-04-27 09:11:53 ZIP code Chicago metropolitan area Geography of the United States Chicago Address DEC Alpha Illinois ARM architecture Instruction set architectures Geography of Illinois Postal system
294	EN164: Design of Computing Systems Lecture 20: Processor / ILP 1 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:54 Parallel computing Classes of computers Central processing unit Superscalar Very long instruction word Hazard Instruction set Slot NOP Computer architecture Computing Computer engineering
295	Exploiting Locality to Improve Circuit-level Timing Speculation Jing Xin, Northwestern University and Russ Joseph, Northwestern University Abstract—Circuit-level timing speculation has been proposed as a technique to r Add to Reading List Source URL: users.eecs.northwestern.edu Language: English - Date: 2010-04-13 16:41:18 Central processing unit Computer memory Instruction set architectures CPU cache Cache Microarchitecture Intel Core DEC Alpha Computer architecture Computer hardware Computer engineering
296	Version 1 Open The Hex 8 Architecture David May: February 21, 2014 Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-02-21 06:51:57 Computing Instruction set architectures Central processing unit Instruction set Pointer
297	Symantec PGP Cryptographic Engine FIPSSecurity Policy Add to Reading List Source URL: csrc.nist.gov Language: English - Date: 2015-05-21 10:19:50 Advanced Encryption Standard AES instruction set X86 architecture FIPS 140-2 Cryptographic hash function FIPS 140 Key Wrap Crypto++ Pretty Good Privacy Cryptography Cryptography standards Cryptographic software
298	Version 1.0 Concurrent/Parallel Processing David May: April 9, 2014 Introduction Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-04-09 06:19:05 Central processing unit Parallel computing Classes of computers Microprocessors CPU cache Superscalar Cell Instruction set Branch predictor Computer architecture Computing Computer hardware
299	KCoFI: Complete Control-Flow Integrity for Commodity Operating System Kernels John Criswell, Nathan Dautenhahn, and Vikram Adve Department of Computer Science University of Illinois at Urbana-Champaign Email: {criswell,d Add to Reading List Source URL: sva.cs.illinois.edu Language: English - Date: 2014-03-30 11:43:41 Process Instruction set architectures Interrupt handler Kernel Operating system Thread Interrupt flag INT Ring Computer architecture Interrupts X86 instructions
300	Version 1.0 X and Hex David May: May 6, 2014 The X Language Add to Reading List Source URL: www.cs.bris.ac.uk Language: English - Date: 2014-05-06 09:48:01 Algebra Machine code Mathematical notation Operand Logical connective Instruction set DEC Alpha IJVM PILOT Computer architecture Computing Instruction set architectures

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